test/prettify/PrettifyTest/result/vhdl.txt

`KWDlibrary`END`PLN ieee`END`PUN;`END`PLN
`END`KWDuse`END`PLN ieee`END`PUN.`END`PLNstd_logic_1164`END`PUN.`END`KWDall`END`PUN;`END`PLN
`END`KWDuse`END`PLN ieee`END`PUN.`END`PLNnumeric_std`END`PUN.`END`KWDall`END`PUN;`END`PLN

`END`COM-- A line comment`END`PLN
`END`KWDentity`END`PLN foo_entity `END`KWDis`END`PLN

  `END`KWDgeneric`END`PLN `END`PUN(`END`COM-- comment after punc`END`PLN
    a `END`PUN:`END`PLN `END`TYPnatural`END`PLN `END`PUN:=`END`PLN `END`LIT42`END`PUN;`END`PLN
    x `END`PUN:`END`PLN `END`TYPreal`END`PLN `END`PUN:=`END`PLN `END`LIT16#ab.cd#-3`END`PLN
  `END`PUN);`END`PLN
  `END`KWDport`END`PLN `END`PUN(`END`PLN
    clk_i `END`PUN:`END`PLN `END`KWDin`END`PLN  `END`TYPstd_logic`END`PUN;`END`PLN
    b_i   `END`PUN:`END`PLN `END`KWDin`END`PLN  `END`TYPnatural`END`PLN `END`KWDrange`END`PLN `END`LIT0`END`PLN `END`KWDto`END`PLN `END`LIT100`END`PUN;`END`PLN
    c_o   `END`PUN:`END`PLN `END`KWDout`END`PLN `END`TYPstd_logic_vector`END`PUN(`END`LIT5`END`PLN `END`KWDdownto`END`PLN `END`LIT0`END`PUN);`END`PLN
    \a "name"\ `END`PUN:`END`PLN `END`KWDout`END`PLN `END`TYPinteger`END`PLN  `END`COM-- extended identifier`END`PLN
  `END`PUN);`END`PLN

`END`KWDend`END`PLN `END`KWDentity`END`PLN foo_entity`END`PUN;`END`PLN

`END`KWDarchitecture`END`PLN foo_architecture `END`KWDof`END`PLN foo_entity `END`KWDis`END`PLN
  `END`KWDsignal`END`PLN bar_s `END`PUN:`END`PLN `END`TYPstd_logic_vector`END`PUN(`END`LIT2`END`PLN `END`KWDdownto`END`PLN `END`LIT0`END`PUN);`END`PLN
`END`KWDbegin`END`PLN
  
  bar_s `END`PUN<=`END`PLN `END`STRb"101"`END`PUN;`END`PLN

  dummy_p `END`PUN:`END`PLN `END`KWDprocess`END`PLN `END`PUN(`END`PLNclk_i`END`PUN)`END`PLN
  `END`KWDbegin`END`PLN
    `END`KWDif`END`PLN b_i `END`PUN=`END`PLN `END`LIT1`END`PLN `END`KWDthen`END`PLN
      c_o `END`PUN<=`END`PLN `END`PUN(`END`KWDothers`END`PLN `END`PUN=>`END`PLN `END`STR'0'`END`PUN);`END`PLN
    `END`KWDelsif`END`PLN rising_edge`END`PUN(`END`PLNclk_i`END`PUN)`END`PLN `END`KWDthen`END`PLN
      c_o `END`PUN<=`END`PLN `END`STR"1011"`END`PLN `END`PUN&`END`PLN bar_s`END`PUN(`END`LIT1`END`PLN `END`KWDdownto`END`PLN `END`LIT0`END`PUN);`END`PLN
    `END`KWDend`END`PLN `END`KWDif`END`PUN;`END`PLN
  `END`KWDend`END`PLN `END`KWDprocess`END`PLN dummy_p`END`PUN;`END`PLN

`END`KWDend`END`PLN `END`KWDarchitecture`END`PLN foo_architecture`END`PUN;`END